The present invention relates generally to semiconductor memory devices, and in particular, the present invention relates to an architecture, package orientation and assembly of semiconductor memory devices.
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM refers to read and write memory; that is, you can repeatedly write data into RAM and read data from RAM. This is in contrast to ROM (read-only memory), which generally only permits the user in routine operation to read data already stored on the ROM. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of ROM that holds instructions for starting up the computer. Unlike RAM, ROM generally cannot be written to in routine operation. An EEPROM (electrically erasable programmable read-only memory) is a special type of non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modern PCs have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU""s bus and is capable of running at 100 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAMs can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
Many SDRAM devices are housed in packages that have an industry-standard pin layout and are of specified lengths and widths, such as a TSOP (thin, small-outline package) having a width of about 400 mils and a length dependent upon the number of pins. Memory chips in known TSOP memory packages have been oriented lengthwise within the package, as illustrated in FIG. 1A, and orthogonally within the package, as illustrated in FIG. 1B. FIGS. 1A and 1B depict industry-standard pin layouts for 44-pin SDRAM TSOP packages.
In the assembly depicted in FIG. 1A, memory chip 60 is oriented lengthwise within the package 62 with the major axis of the memory chip 60 extending substantially parallel to the major axis of the package 62. In the memory chip 60 of FIG. 1A, chip bond pads are located at opposite ends of the memory chip 60. An end will be referred to as opposite another end when the ends are separated by the minor axis. Address chip bond pads 66 are located at a first end of memory chip 60 while data chip bond pads 68 are located at a second end of memory chip 60. The address chip bond pads 66 are connected to the address pins A0-A10 and BA of the package 62 in a conventional manner. The data chip bond pads 68 are connected to the data pins DQ0-DQ7 in a conventional manner. To simplify the drawings, remaining chip bond pads, such as clock and control signal chip bond pads CLK, CKE, DQM, RAS#, CAS#, WE# and CS#, and power input chip bond pads VCC, VSS, VCCQ and VSSQ, are not labeled in FIG. 1A.
As shown in FIG. 1A, the address chip bond pads 66 of memory chip 60 are located adjacent the address pins A0-A10 near one end 70 of the package 62, with some of the address pins located at one side 74 of the package 62 and the remaining address pins located at the other, opposite side 76 of the package 62. A side will be referred to as opposite another side when the sides are separated by the major axis. The data chip bond pads 68 are located adjacent the data pins DQ0-DQ7 near one end 72 of the package 62, with some of the data pins located at one side 74 of the package 62 and the remaining data pins located at the other, opposite side 76 of the package 62.
In the assembly depicted in FIG. 1B, memory chip 60 is oriented orthogonally within the package 62 with the major axis of the memory chip 60 extending substantially perpendicular to the major axis of the package 62. In the memory chip 60 of FIG. 1B, chip bond pads are located between the banks of memory arrays, or memory banks 64, located on memory chip 60. Address chip bond pads 66 are located adjacent a first memory bank 640 while data chip bond pads 68 are located a adjacent a second memory bank 641. The address chip bond pads 66 are connected to the address pins A0-A10 and BA of the package 62 in a conventional manner. The data chip bond pads 68 are connected to the data pins DQ0-DQ7 in a conventional manner. To simplify the drawings, remaining chip bond pads, such as clock and control signal chip bond pads CLK, CKE, DQM, RAS#, CAS#, WE# and CS#, and power input chip bond pads VCC, VSS, VCCQ and VSSQ, are not labeled in FIG. 1B.
As shown in FIG. 1B, the address chip bond pads 66 of memory chip 60 are located adjacent the address pins A0-A10 near one end 70 of the package 62, with some of the address pins located at one side 74 of the package 62 and the remaining address pins located at the other, opposite side 76 of the package 62. Likewise, the data chip bond pads 68 are located adjacent the data pins DQ0-DQ7 near one end 72 of the package 62, with some of the data pins located at one side 74 of the package 62 and the remaining data pins located at the other, opposite side 76 of the package 62.
Undesirable propagation delays may be introduced in a memory assembly between the memory device and the address pins or data pins of the memory package as a result of high RC (resistive/capacitive) time constants between chip bond pads and their associated circuitry. Placement of the chip bond pads thus generally limits placement of the access circuitry. As memory devices become larger, thus containing larger arrays and/or more memory banks, these considerations become more critical.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate architecture and assembly of semiconductor memory devices.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
The invention includes memory assemblies and their components having memory chips with data chip bond pads and address chip bond pads segregated in opposite quadrants of the memory chips. Various embodiments include flash memory assemblies containing non-volatile flash memory cells and synchronous flash memory assemblies containing non-volatile flash memory cells and having access commands synchronized to a system clock.
For one embodiment, the invention provides a memory chip. The memory chip includes a plurality of memory banks having a major axis substantially parallel with a first side of the memory chip. The memory chip further includes data chip bond pads located adjacent the first side of the memory chip in a first quadrant of the memory chip. Each data chip bond pad of the memory chip is located in the first quadrant of the memory chip. The memory chip still further includes address chip bond pads located adjacent a side of the memory chip opposite the first side and in a quadrant of the memory chip opposite the first quadrant. Each address chip bond pad of the memory chip is located in the quadrant of the memory chip opposite the first quadrant. Thus, for such embodiments, data chip bond pads and address chip bond pads occupy only two, opposite quadrants of the memory chip.
For another embodiment, the invention provides a memory chip. The memory chip includes a multiple-bank memory array having a major axis substantially parallel with a first side of the memory chip. The banks of the memory array have the same orientation and the input/output gating circuitry for each bank is located adjacent the first side of the memory chip. Data chip bond pads for the memory chip are interposed between the input/output gating circuitry and the first side of the memory chip in a first quadrant of the memory chip. The address chip bond pads are located adjacent a side of the memory chip opposite the first side and in a quadrant of the memory chip opposite the first quadrant.
For yet another embodiment, the invention provides a memory chip. The memory chip includes a substrate having a memory device fabricated thereon. The memory device includes memory banks having address inputs and data inputs/outputs. A first row of chip bond pads is fabricated on the substrate in a first end and on a first side of the memory chip. A second row of chip bond pads is fabricated on the substrate in a second end of the memory chip opposite the first end and on a second side of the memory chip opposite the first side. Each of the data inputs/outputs is coupled to a chip bond pad in the first row of chip bond pads. Furthermore, each of the address inputs is coupled to a chip bond pad in the second row of chip bond pads.
For a further embodiment, the invention provides a lead-over-chip leadframe. The leadframe includes a first plurality of leads extending from a first side of the leadframe and originating in a first quadrant of the leadframe, wherein the first plurality of leads terminates in the first quadrant of the leadframe. The leadframe further includes a second plurality of leads extending from the first side of the leadframe and originating in a second quadrant of the leadframe, wherein the second plurality of leads terminates in a third quadrant of the leadframe. The leadframe still further includes a third plurality of leads extending from a second side of the leadframe and originating in the third quadrant of the leadframe, wherein the third plurality of leads terminates in the third quadrant of the leadframe. The leadframe still further includes a fourth plurality of leads extending from the second side of the leadframe and originating in a fourth quadrant of the leadframe, wherein the fourth plurality of leads terminates in the first quadrant of the leadframe.
For a still further embodiment, the invention provides a memory assembly. The memory assembly includes a memory package having a plurality of interconnect pins, wherein the plurality of interconnect pins comprises a first plurality of data pins located on a first side of the memory package, a second plurality of data pins located on a second side of the memory package, a first plurality of address pins located on the first side of the memory package, and a second plurality of address pins located on the second side of the memory package. The memory assembly further includes a lead-over-chip leadframe having a plurality of leads coupled to the plurality of interconnect pins in a one-to-one relationship. The memory assembly still further includes a memory chip. The memory chip includes a plurality of memory banks having a major axis substantially parallel with a first side of the memory chip. Each of the plurality of memory banks has the same orientation and each of the plurality of memory banks has input/output gating circuitry located adjacent the first side of the memory chip. The memory chip further includes a first plurality of data chip bond pads interposed between the input/output gating circuitry and the first side of the memory chip in a first quadrant of the memory chip, a second plurality of data chip bond pads interposed between the input/output gating circuitry and the first side of the memory chip in the first quadrant of the memory chip, a first plurality of address chip bond pads located adjacent a side of the memory chip opposite the first side and in a quadrant of the memory chip opposite the first quadrant, and a second plurality of address chip bond pads located adjacent the side of the memory chip opposite the first side and in the quadrant of the memory chip opposite the first quadrant. The first plurality of data chip bond pads is coupled to the first plurality of data pins through leads of the leadframe, the second plurality of data chip bond pads is coupled to the second plurality of data pins through leads of the leadframe, the first plurality of address chip bond pads is coupled to the first plurality of address pins through leads of the leadframe, and the second plurality of address chip bond pads is coupled to the second plurality of address pins through leads of the leadframe.
For one embodiment, the invention provides a synchronous flash memory chip. The memory chip includes a plurality of memory banks containing non-volatile flash memory cells. The plurality of memory banks may have the same orientation such that each of the plurality of memory banks has input/output gating circuitry located adjacent a first side of the memory chip. The memory chip further includes a command execution logic coupled to the plurality of memory banks for receiving a system clock input signal and for generating commands to control operations performed on the plurality of memory banks. The commands are synchronized to the system clock input signal. The memory chip further includes a plurality of data inputs/outputs coupled to the plurality of memory banks, a plurality of address inputs coupled to the plurality of memory banks, a plurality of data chip bond pads coupled to the plurality of data inputs/outputs, and a plurality of address chip bond pads coupled to the plurality of address inputs. The plurality of data chip bond pads are located adjacent the first side of the memory chip in a first quadrant of the memory chip. The plurality of address chip bond pads is located adjacent a second side of the memory chip opposite the first side and in a third quadrant of the memory chip opposite the first quadrant.
For yet another embodiment, the invention provides a synchronous flash memory assembly. The memory assembly includes a memory package having a plurality of interconnect pins having a pin layout substantially similar to an industry-standard SDRAM layout, a lead-over-chip leadframe having a plurality of leads coupled to the plurality of interconnect pins in a one-to-one relationship, and a synchronous flash memory chip. The memory chip includes a plurality of memory banks containing non-volatile flash memory cells, wherein the plurality of memory banks may have the same orientation such that each of the plurality of memory banks has input/output gating circuitry located adjacent a first side of the memory chip. The memory chip further includes a command execution logic coupled to the plurality of memory banks for receiving a system clock input signal and for generating commands to control operations performed on the plurality of memory banks, wherein the commands are synchronized to the system clock input signal. The memory chip further includes a plurality of data inputs/outputs coupled to the plurality of memory banks, a plurality of address inputs coupled to the plurality of memory banks, a plurality of data chip bond pads coupled to the plurality of data inputs/outputs, and a plurality of address chip bond pads coupled to the plurality of address inputs. The data chip bond pads are located adjacent the first side of the memory chip in a first quadrant of the memory chip. The address chip bond pads are located adjacent a second side of the memory chip opposite the first side and in a third quadrant of the memory chip opposite the first quadrant. A first portion of the plurality of data chip bond pads is coupled to data pins of a first side of the memory package through leads of the leadframe. A remaining portion of the plurality of data chip bond pads is coupled to data pins of a second side of the memory package through leads of the leadframe. A first portion of the plurality of address chip bond pads is coupled to address pins of the first side of the memory package through leads of the leadframe. A remaining portion of the plurality of address chip bond pads is coupled to address pins of the second side of the memory package through leads of the leadframe.
The invention further provides memory chips, leadframes and assemblies of various scope.